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The AT93C86A is enabled through the Chip Select pin (CS), and accessed via a three-
wire serial interface consisting of Data Input (DI), Data Output (DO), and Shift Clock
(SK). Upon receiving a Read instruction at DI, the address is decoded and the data is
clocked out serially on the data output pin DO. The Write cycle is completely self-timed
and no separate Erase cycle is required before Write. The Write cycle is only enabled
when the part is in the Erase/Write Enable state. When CS is brought “high” following
the initiation of a Write cycle, the DO pin outputs the Ready/Busy status of the part. The
AT93C86A is available in a 2.7V to 5.5V version.
Absolute Maximum Ratings*
Operating Temperature ......................................? 55 ° C to +125 ° C
Storage Temperature .........................................? 65 ° C to +150 ° C
Voltage on any Pin
with Respect to Ground ........................................ ? 1.0V to +7.0V
Maximum Operating Voltage .......................................... 6.25V
DC Output Current........................................................ 5.0 mA
Figure 1. Block Diagram
Vcc
GND
*NOTICE:
Stresses beyond those listed under “Absolute
Maximum Ratings” may cause permanent dam-
age to the device. This is a stress rating only and
functional operation of the device at these or any
other conditions beyond those indicated in the
operational sections of this specification is not
implied. Exposure to absolute maximum rating
conditions for extended periods may affect
device reliability
MEMORY ARRAY
ORG
DI
2048 x 8
OR
1024 x 16
DATA
REGISTER
ADDRESS
DECODER
OUTPUT
BUFFER
MODE
DECODE
CS
LOGIC
SK
CLOCK
GENERATOR
DO
Note:
2
When the ORG pin is connected to Vcc, the x 16 organization is selected. When it is connected to ground, the x 8 organization
is selected. If the ORG pin is left unconnected and the application does not load the input beyond the capability of the internal 1
Meg ohm pullup, then the x 16 organization is selected.
AT93C86A
3408H–SEEPR–1/07
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